Chip design in the Cloud

Biggest Challenges in FPGA Design

2012-01-20T00:22:00.001-08:00

A poll on the challenges associated with FPGA design in an FPGA discussion group on LinkedIn caught my attention recently. Conducted by Cuong Nguyen from EDA Direct, it drew several lengthy comments.

Poll: FPGA Design Challenges

My vote went to Timing Closure - definitely one of the most frustrating and time-consuming classes of problems for me. Unlike functional bugs, timing problems can be rather unpredictable because there are more dependencies on the rest of the system, and also because different synthesis and place-and-route tools have their own unique options that can improve / worsen timing scores unexpectedly. This seems especially true when a design exceeds ~75% utilization and above. Which reminds me of a restriction placed on the FPGA team at a user's company where, at the code development phase, no design was allowed to exceed 70% total utilization.

The closer it gets to the deadline, the more urgent it is for the designer to find a timing solution without changing too much of the design. Upstream changes are rarely welcomed so if a tool option can result in positive slack, that would be very much preferred.

One rather brute-force approach that I've used before was to run a design against almost every conceivable tool option and just select the best results. Of course, that's assuming one has sufficient licenses, enough servers and suitable scripting experience, otherwise it is going to be very time- and resource-consuming. Over time, we've figured out a more optimized set of options that perform well for different designs, and are now pairing those with cloud computing resources to get a good blend of options vs tools+hardware. This approach has been working very well so far and we're improving it as we get more designs.

What's the most challenging thing that you've faced in FPGA design?

- harnhua

Private or Public clouds? Or why not both?

2011-12-15T04:49:00.000-08:00

(This post was sparked by an interesting email conversation with a user. I promised that I will post my views in a new blog article, so here it is)

Why doesn't Plunify yet provide a hybrid solution, a solution that works seamlessly on private and public clouds? For those who are finding out about us for the first time, Plunify helps FPGA designers use the cloud to achieve their design objectives in a much shorter time, such as achieving timing closure, exploring different constraints in parallel or simply regression testing. To do this, Plunify uses Amazon Web Services (public cloud) and we are an AWS solutions provider. Click here to if you're interested in how we do it

Why public clouds for us
There are many definitions of cloud computing out there. The term, "cloud computing," itself is rather over-hyped and everyone wants a piece of it in his/her value proposition. The one definition that really bugs me is that cloud computing is just a massive shared drive. Although that is not totally wrong, it sounds like we've gone back to the days of mainframes and thin clients, and, in my opinion, misses the most important point of any application built with cloud computing technologies - scalability.

Scalability means that you can instantly start 1 server or 100 servers at the click of button or a script. It also means that you can store 5Mb or 50GB on the fly.

This brings me to the first difference between a private cloud and public cloud. With a private cloud, you are limited to the number of servers you own. And unless you are Intel or Cisco or the government of a country, you will have a scaling limitation. So for most of us, converting that to a private cloud, means that we are splitting up a limited pool of resources using virtualization, into even smaller pools of resources. That doesn't make sense to me at all because compiling a FPGA design is often a compute-intensive process. Part of the idea of cloud computing is to increase your available resources as well, not just keeping them at the same level.

Costs + Hidden Costs + Maintenance
You might say, "Hold on, why can't I just buy more servers for my private cloud?"
Sure, if you are Intel, Cisco or someone who can afford to buy in bulk and get a juicy discount.
On top of that, you have to take into account that 43% of the costs are hidden - those rear their ugly heads in configuration, maintenance, power, cooling, climate-control, backup and many other overheads.

Estimating your needs
If you still want to buy, how many more servers will you buy? Meeting your computing demand is not an exact science. Unless we measure every minute of our usage, we can only make an estimate. If you over-estimate, you will be wasting idling compute resources. If you underestimate, it will delay your development process at critical phases. It is practically impossible to be perfect.

Cloud computing solves this problem with scalability but it can be a double-edged sword. If you normally underestimate your demands, you may pay more overall because in reality, you actually need the additional resources on a regular basis. But if you are blessed with a fat budget and can afford to overestimate your demand, you may find yourself paying less. No matter which side you are on, the important thing is that cloud computing is a fairer allocation and better use of your company's resources.

Why not a hybrid?
For the short term, it might seem attractive and prudent to convert your local pool of servers into a private cloud. You've already bought your servers, right? Why not utilize them to the max? Yes, you should, if you have a huge, established datacenter, equipped with Mission Impossible-style physical security and network equipment.

If you don't, here is why you should reconsider trying to implement a private or hybrid cloud.
It is hard to replicate fully what has already been done in the public cloud, in a private setting. There is software like Eucalyptus, which does a good job of creating hybrid clouds. Even so, the effort to make sure that both private-facing and public-facing ends work seamlessly, coupled with our cloud application platform, is not going to be trivial. Eventually support and maintenance cost will also increase. Issues such as who is responsible for the server or network if there is an outage, replacement of hardware and reconfiguration becomes fuzzy as well. Support costs may eclipse any cost savings from running a hybrid cloud in the first place. A lot of time will be spent dealing with such issues, especially if the IT department is also you - the design engineer.

Best or worst of both worlds?
We aren't against the idea of hybrid clouds. If your local datacenter is not of sufficient size, making the effort to transit to a hybrid does not seem to be worth it, especially if you are doing it just for chip design. We don't want you to be in a situation where instead of enjoying the best of both worlds, you are suffering from the worst of both worlds.

To sum up, we're open to any solution as long as it makes sense for our customers. Making a good, elegant and affordable solution is not easy and will require rigorous testing and support effort. For now, we will concentrate on ensuring our solutions on the public cloud is secure, safe and easy to use.

Feel free to comment or lob any questions/disagreements to tellus@plunify.com

- Kirvy

Coming to a location near you!

2011-12-06T22:05:00.001-08:00

Event: Accelerate TTM using Cloud Computing

2011-10-19T02:40:00.000-07:00

At an industry event last Friday (Oct 14th 2011), we had the chance to present a talk on, "What Can FPGA Designers Do With Personal Data Centers?" and demonstrate our new cloud-based approach to achieving timing closure for an FPGA design.

Opening

Mike Holt, Vice-President of the Singapore Semiconductor Industry Association, opened the event with a look at this "cloud thingie" and how rising complexity of chip designs cause hardware designers problems in design and verification processes. Consequences include expensive product delays and bigger development bills. The cloud approach is increasingly seen as a good solution.

Background on cloud computing

Kingsley Wood from Amazon Web Services (AWS) continued along this vein with an introduction to cloud computing, highlighting AWS features that might be of interest to a solutions provider like us. Specific to the semiconductor industry where compute-intensive tasks, large file sets and complex workflows abound, and with major EDA vendors already using the AWS infrastructure to provide some services, cloud computing has certainly become significant for chip design.

Members of the audience were curious as to how annual licensing schemes for enterprise software have been changed into SaaS models in other industries, and how AWS and solution providers of cloud computing applications deal with data losses.

IC Design-specific issues

Meenu Sarin from VLSI Consultancy was up next, talking about specific challenges such as portability of design data in multi-vendor flows, standardization of IP and difficulties in scaling design processes. She also explored concerns about the cloud such as security and bandwidth, and raised the question of which organizations are best-suited to manage a cloud resource in the semiconductor industry where there are so many different stakeholders.

Personal data center for FPGA design

What does a designer think of when s/he sees the term, "data center for FPGA design"?
We proposed the model of a dedicated resource with the requisite components for an FPGA design:

IP to use in the design
Tools (and licenses) to crunch the design
Servers to run the tools
Collaboration mechanisms e.g. source control, permissive sharing
Portability of data (standardization) if/when a multi-vendor approach is desired

And from a dollars-and-cents point of view:

Pay-as-you-use

The above framework is by no means groundbreaking, as since the 1960s, our industry has seen mainframes and supercomputers in a centralized processing model evolve into dispersed workstations and distributed grid computing networks, all before cloud computing came into fashion. However, to us, scalability is the most attractive thing about the cloud, the best thing since sliced cloud.

Demo

I then proceeded to show, "live", how an FPGA design that fails timing can be processed in parallel, using a cloud managed by Plunify, to achieve timing closure.

Linux PC connected to the Internet via a Wifi network
Altera Quartus II 10.0 SP1

This is meant to mimic a typical designer's setup

OR1200 32-bit microprocessor
Altera Stratix III L50 FPGA
Plunify plugin scripts for Quartus

Initially, there's a Timing Violation (Slack) of -0.519 ns

Using a cloud-based approach, our tool calculates a series of parameters that will help the place-and-route tool, and then from the Linux PC, runs all these iterations in parallel.

Out of 35 iterations, each taking about 30 minutes, two iterations met timing.

Timing closure was achieved at 0.093 ns, 0.011 ns. *phew*!
Summary: http://www.plunify.com/reports/timingAnalysis.php?or1200_top=1
Only iterations "dse_point_19" and "dse_point_26" had the passing timing results. (Mouse-over the "i" icons in the table to see which parameters were used in each iteration (revision).

The demo went well, (to my relief - presenter anxiety!), and immediately the audience could see our cloud-based approach got to timing closure in almost 1/20 of the amount of time that would have been spent.

Let us know how useful this feature is - tellus (at) plunify (dot) com

Productivity features in FPGA tools

Wai-Leng Cheong, Sr Channel Manager at Altera proceeded to describe incremental compilation features of the Quartus II software, and how it can be used as a form of collaboration by design teams working at different locations. Among other things, the Quartus software makes use of multiple CPU cores which makes it even more well-suited to a cloud environment.

Panel Discussion

The last formal item for the event was a discussion where we talked about more high-level issues and the implications of cloud computing in the industry for end-users and vendors alike. Topics included:

Companies are finding different ways to speed up development, for example, improving software algorithms in tools, using hardware emulation platforms standalone or to augment software simulations, streamlining workflows and procedures, etc.
Cloud computing, though much hyped in general, is one way to improve time-to-market, and its economies of scale makes it especially compelling.
Lack of a common design methodology, data standards are some of the deeper issues that cause delays in the semiconductor industry.
Changes to the current annual licensing model must be justifiable in order to persuade tool vendors to switch to a hourly / daily / weekly / monthly / pay-as-you-use model. However the longer that process takes, the riskier it might become for vendors in the long run because the costs of sustaining the annual licensing model are becoming more and more daunting. EDA vendors have been facing slowing growth for a few years now.
Besides solutions providers, are foundries the natural candidates for the managers of a cloud solution?

Because the economies of scale make so much more sense for both vendors and users alike, we have to work hard to put together scenarios whereby a change from the traditional annual licensing model to an hourly / daily / weekly / monthly model does not erode the bottom-line for companies which have been relying on the former for so long.

It was a pleasure to be a part of this event organized by the Singapore Semiconductor Industry Association (SSIA) and to meet fellow semiconductor professionals and hardware designers from local schools, research labs and companies.

- harnhua

Safer in the Cloud?

2011-09-27T18:56:00.000-07:00

Security has long been one of the first and most pressing questions for the cloud. Users and business owners are naturally wary about placing sensitive data in the hands of a 3rd-party. This is especially true for the semiconductor chip design industry, and rightly so.

However, one point which is gaining acceptance is that if one is concerned about security and does not have the resources to constantly monitor and implement the latest safeguards, why not entrust security to a dedicated provider? This trusted provider is industry-certified and spends all its time worrying about protecting their customers' data because simply, they will go out of business if that data is compromised.

As described in the articles below, small and medium businesses can probably benefit most from adopting cloud solutions.

"Small and medium businesses are insane not to leverage the advantages of cloud computing,"

No system is foolproof, and we will hear about data leaks from time to time, but from experience, it seems reasonable to say that specialized providers like Amazon are often better-positioned to handle security in many cases.

Cloud computing & software piracy: From prevention and mitigation to win-win?

2011-08-30T20:15:00.000-07:00

Came across an article on EDN that talks about software piracy in EDA land.
Apparently 30% to 40% of all EDA software use is via pirated licenses.
Imagine what this means in terms of lost revenue to EDA vendors, and to endusers, it might be argued that a rival design team is spending far less on far more software licenses - and getting their products out to market much quicker.

Sounds like an echo of problems plaguing the general software, music and film industries?
If fewer and fewer people buy legitimate licenses (software, songs, movies etc.) then perhaps fewer EDA vendors (artists) will be able to make a good living, and there might eventually be less EDA software (works of art) for endusers.

The cloud has been talked about as a potential means of prevention.
According to a Cadence spokesperson,

"When we have software as a service, either at our own cloud or an external Cadence-certified cloud, we basically retain control of the environment, including the licensed server. Licensing becomes a non-issue."

There are few doubts as to whether a cloud computing solution will help mitigate software piracy, given its degree of control and flexibility for both vendors and endusers.

But there is a deeper side of the issue that we shouldn't ignore, and that is when there is an arms race, both sides would do better to embrace each other rather than compete to see who can create the better licensing mechanism or more elegant key crack.
As a Chinese saying goes, “道高一尺魔高一丈” - loosely translated as, "When the priest advances one foot, the devil advances by ten" - a perpetual arms race, essentially, which is probably going to bleed the vendors dry and cause inefficiencies for legitimate users in the long run.

What I'm trying to express is, there must be a more effective middle ground where EDA vendors and endusers can come together in a win-win situation.
The cloud is a wonderful place to meet in the middle, affording each side:

effective means of control and usage
smooth trial and feedback
efficient delivery and support on a large (in EDA anyway) scale (Larry Disenhof, group director of export compliance and government affairs at Cadence, estimates that one third of such piracy could be turned into revenue)

What are your thoughts?

Harnhua

Maximizing parallelism in FPGAs - a discussion

2011-08-21T20:31:00.000-07:00

Came across an interesting discussion on FPGAs and parallelism on LinkedIn:

The original poster, Karl Stevens, starts off by asking,

In the context of an FPGA, parallelism is an important item. Which kinds of parallelism apply and how much performance is gained? Compared to what?
Most kinds of parallelism apply to cpu's. FPGAs can do register transfers and ALU functions in parallel, that is if there are multiple alu's available. FPGA is a special purpose processor?

and goes on to elaborate:

The kinds of parallelism that I have found:
bit level -- simply make the data wider.
instruction level -- involves pipelining if the process is done in stages
data -- same calculation on different sets of data -- implies parallel; ALU's, data sources
task -- different calculation on same or different sets of data -- same data implies shared data

These are conceptual and not precise.
Data width is a non issue.
Pipelining usually implies an "instruction" kind of control where the execution/assign step depends on an operator code and the other stages get the data and dispose of the result.
On chip memory is so fast that a dual port ram can read and write simultaneously in about a third of a typical clock interval. Staging may only apply when external memory is used.
Parallel data -- use the same controls for parallel alu's and memories
Parallel tasks -- repeat the above for the specific task.
The synthesis tools focus on extracting "parallelism" from an imperative program and so far are reported to be almost as good as a college student using classroom assignments as inputs.
When HLS. ESL. or whatever mature, what will be the measurable benefit? Is it the pie in the sky dream that C programmers can design FPGAs? Or will it be performance? How much?

In terms of architecture, FPGAs certainly seem well-suited for parallelism. They are like blank slates; you are free to design the logic, balance out the area and speed requirements plus the interfacing to external logic and you're done.

Highlighting some comments:

"Okay, the marketing people tell me that I just throw as much logic at my problem as I like, especially for DSPs, however that depends 100% on how my design works with the rest of the system. So it's never as simple as that, isn't it?"
"What are the trade-offs between pipelining and parallelism? For example, in a mixer design where you have data sampling followed by processing via an FFT, and then data output?"
"Do these questions apply similarly to software architects when designing their systems?"
"Does flexibility to place your logic kill performance?"
"Would an array of general purpose processors offer similar performance benefits as an array of FPGAs, given that processor technology has been pretty much commoditized?"

Varun Nagpal stated some ways to think about implementing algorithms:

Now algorithms have many associated dimensions which can help to decide whether one needs to make a dedicated circuit architecture on FPGA/ASIC or if a specific class of processor can be used
-. Decomposability: iterative, recursive.
-. Control intensive i.e. react to events, data intensive i.e. transforms input to output. or a combination
-. Data storage requirements and data precision.
-. Repetition or frequency of specific operations
-. latency(ns,us,ms,s) vs throughput(MOPS or GOPS or TOPS or POPS)

Mike Field revealed some results that he had gotten for a Mandelbrot design:

I built a Mandelbrot Fractal viewer running at 100MHz on a Spartan-3E. It is inherently parallel, as each pixel can be computed in isolation. It is most probably perfectly sutied for FPGA implementation.

It computed “deep” images (those with high average loop iterations per pixel) to within a few % of a single AMD 2GHz core. On a larger FPGA with more 18x18 multipliers the pipeline depth could be doubled or tripled, with a corresponding scaling of throughput. For “shallow” images the throughput is hampered by the limited RAM write bandwidth (it was also servicing a 1024x768 VGA display) so many completed calculations being sent through the pipeline for another round.

Speed comes from being able to pipeline the calculation. In software the it is a loop of a dozen or so instructions – a bit complex multiply, something close to a complex abs() function, two comparisons an 8bit increment, and a jump. On the FPGA I implemented it as a 12 stage pipeline, which gives performance of one loop iteration per clock Careful selection of data representation also allows the best use of the FPGA hardware (36 bit fixed point with external sign), where on a CPU you only get the choice of “double” or “float”.

Depending on your point of view, this is either “Just as fast as an AMD CPU” (which is still pretty good), or 20x times faster (on a per clock cycle basis). It is also very green – it has superb “compute per watt” at less than 2.5W compared to a desktop PC.

And finally, a pearl of FPGA wisdom from a wise man that Mike met, "FPGA design is the art of balancing size, memory and speed" ; )

- Harnhua

Retrofitting our platform and ourselves

2011-07-27T23:48:00.000-07:00

We are glad to announce significant upgrades to our cloud management platform!

Although the frontend online interface looks almost the same, the backend has become a much stronger beast. Essentially we restructured the code to make the platform even more scalable and configurable.

Inspired by the recent spate of hacking activities, we also added a lot of security enhancements - paranoia perhaps, but absolutely necessary.
Without revealing the gory details, these include using better encryption and inserting additional encryption at all levels of the platform. We applied Amazon Web Services APIs to ensure that the walls between each user's access rights are higher than before. We made it such that Virtual Private Networks add another layer of protection when necessary. Well, one can never stop enhancing security.

Finally, we will revamp our website.
We have been reading lots of stuff about us (LinkedIn), and our website should better reflect Plunify's value proposition.

As a startup, we have to get this right.
"Your startup is essentially an organization built to search for a repeatable and scalable business model" - Steve Blank

Thanks for reading and let us know your thoughts.

Kirvy

The Cloud a better match for FPGAs?

2011-04-01T00:41:00.000-07:00

A few days ago, Synopsys announced that they are preparing for their tools to make use of cloud computing. Which was a little strange considering comments to the contrary from both Cadence and Synopsys just a couple of months earlier.

"Synopsys Chairman and CEO Aart de Geus told an audience at the company's SNUG San Jose users' group event here Monday that using a "surge" in computing resources would allow designers to run a number of verification simulations in days or weeks that may have taken many months otherwise."

Finally! One of the "big guys" has spoken!
Simply put, it's a gift for us.

To most, the contents of the above article are far more persuasive than 2 guys in a startup trying to convince designers, partners and investors that Cloud Computing represents a huge opportunity for EDA.

Managed properly, the Cloud promises remarkable productivity gains.
The Cloud is actually not that scary once one understands it.

Mr. de Geus does not seem to be sure of the business model for now; perhaps he is concerned how an SaaS solution which charges by per hour is going to cannibalize their per license software revenues. This may be a hurdle for big companies like Synopsys and Cadence.

FPGA companies in comparison do not have this problem. Their revenue is primarily driven by chip sales. Hence Cloud Computing is a better fit for FPGAs.

How to run logic simulations online!

2011-01-10T23:16:00.000-08:00

Need to run Verilog or VHDL simulations but don't have the right software installed?
Simulations running a little too slowly?

With Plunify's online simulation service (and in future, synthesis and implementation), now all you need are:

An Internet connection and any major web browser.
The ability to run a Perl script on your PC (see detailed requirements below).
A user configuration file telling us about your simulation (see sample below).
Verilog or VHDL source files.

Here's a VHDL example:

Download the sample:
- a Perl script (platypus.pl),
- the sample user configuration file (adder.cfg); and
- source code (adder.zip).
Extract adder.zip into a local folder.
Edit the username, password, source_folder fields in adder.cfg
(First-time users need to check email and click on an activation link before viewing results).
Run the script: perl platypus.pl --cfg adder.cfg
If it is successful, you should see the following message:

(see below under "Requirements" if you hit errors for missing Perl modules)
Log on at https://www.plunify.com/login.php
Go to Results

That's it.

If the job submission is successful, you will get a notification email after 2-3 minutes.
It takes a little longer to run the first simulation job, but subsequent ones will be faster.

Requirements:

A working installation of Perl and the CPAN modules:
Getopt::Long
Archive::Zip
LWP::UserAgent

Do use mechanisms like the CPAN shell (In Linux, perl -MCPAN -e shell, install Archive::Zip) to install modules.

How it works:

The configuration file contains your details

username = email address as a user name to log on to Plunify
password = user password (> 5 characters), in plain text
jobtype = type of job (currently 'SIM' is the only valid type)
language = Verilog or VHDL (Icarus Verilog or GHDL, pending mixed language support)
source_folder = root folder of directory tree containing source files
toplevel = top level module name
apicode = PLATYPUS, for our internal use

The script sends both your configuration file and your source files to Plunify via a secure connection, and runs your simulation.

Let us know what you think and how we can improve it.

DDT: Are IP cores supposed to work out of the box?

2010-11-24T01:07:00.000-08:00

Too much turkey over the Thanksgiving break would have dulled the senses a little, if not for the sobering arrival of our November's story from a reader in Japan.

(Translated)

"We are a design contractor implementing FPGA projects for clients. In the summer of 2007, we received a request for a system that uses PCI. As we did not have our own PCI IP core at that time, we decided to purchase one from a major IP provider.

The sales engineer kindly gave us a working reference design and development board for that IP core.

However, because of reasons that we never managed to figure out, the PCI core would fail place-and-route, or fail to work in actual hardware at certain times.

After our engineering team debugged it for a month, we finally asked the IP vendor for assistance. Their engineers were very apologetic and tried their best to help, however because their development team was not based in Japan, response was slow.

Eventually, we had to give up on the project and ask the client for their forgiveness.

To this day, we do not know what was wrong with the PCI IP core, but we have since developed our own."

-- "d_oni", design consultant

More than just cheap computing resources

2010-11-15T07:49:00.000-08:00

Many hardware designers whom we spoke with, including investors, students, engineers, regardless of whether they work with ASICs or FPGAs, associate cloud computing with utility or cheap computing power. Instead of spending half a million dollars on servers, networking equipment and maintenance, one can simply use a "rental cloud".

While the benefits are commonly touted, in the digital hardware world, certain attributes like convenience, on-demand scalability and parallel execution of design tasks really come into the fore.

For example, instead of designing, synthesizing, placing and routing a single design with a single set of parameters or constraints, let's try the three most probable design configurations at the same time. Once the compute-intensive tasks are complete, your compute resources can be relinquished to save on maintenance time and effort, and re-acquired when the need arises.

DDT: There are resets and then there are resets...

2010-10-27T21:32:00.000-07:00

Our inaugural DDT story comes from an embedded systems engineer at FPGA vendor X, proving that hey, even FPGA manufacturers have their fair share of design woes.

"It was a windy, somewhat cloudy day in San Jose, at a time when embedded processor blocks in FPGAs were just starting to become popular.

I was tinkering with an ML300 board, which had a Virtex-II Pro FPGA device with a built-in PPC405 processor. A customer's design was loaded onto the board, and that displayed very strange memory behavior.
random read/write errors
software applications crashed at odd places
Sensing a memory problem, we checked the following:
the software application C source code... hmm... nothing seemed wrong
dumping memory at various locations and breakpoints... looked okay
poring over the Verilog/VHDL... worked well on other designs
simulations ran fine- probing the board hardware
power supply... up to spec
voltage levels on the FPGA's pins... checked out okay
Different boards showed the same symptoms so it wasn't a board-specific problem. Essentially, all the checkboxes were being ticked to no avail. But the symptoms persisted and something was obviously wrong. Frustration set in, especially since the ML300 embedded system had been well-used in the field without similar problems.

Finally someone noticed that the errors happened ONLY when the processor underwent a soft reset (hit the reset button instead of power-cycling the board). Bingo. That pointed to the reset states of the modules in the FPGA, and in particular, the processor. And it took a register-by-register comparison of the processor's state after a hard reset versus that after a soft reset to find the bug.

It was a processor firmware bug--a couple of the cache registers weren't initialized properly. On a hard reset, those registers were set to the right values, but on a soft reset... "

-- "Resetter", design engineer

DDT - "Death by Design Thursday"

2010-10-10T22:42:00.000-07:00

When users tell us about what plagues them in their work, we get a lot of different, fascinating responses. Plunify can address some of their problems, but for many, experience, ingenuity and resourcefulness are still the best tools for a developer. Beyond those, perhaps one ends up in the realm of miracles. ; )

So we decided to start "DDT" - "Death by Design Thursday"!

On the last Thursday of the month, we'll put up some of the craziest stories we get about FPGA designers and their projects. The first one will be coming out at the end of this month - 28th Oct.

These can be as simple as how a bug or person delayed your project, or maybe your dog crashed the Place-and-Route that has been running for three days. In any case, we'd love to hear them all! Tell us if you are working on any cool projects involving FPGA as well, especially if you are a hobbyist.

Please send your stories to tellus@plunify.com. Your name and contact details will be kept confidential if you like. Have fun!

Can we trust the Cloud?

2010-09-25T07:11:00.000-07:00

I recently had the pleasure of hearing Aaron Patzer of Mint.com speak at a Founder's Institute event. It was about how Mint was found and their early challenges.
One of the challenges he faced was similar to what we face at Plunify - security and trust

Mint.com helps you manage personal finances. Their interactive, user-friendly software keeps track of your spending, loans, etc.
However you have to key in confidential information such as banking passwords so that Mint can retrieve your data from your financial institutions.

"What! Key in my passwords? You must be joking!" - Yes, that was my initial reaction.
Check out Mint's forum and you will see lots of security-related posts.
I would say that the leap of faith required by Mint's users might be greater than that Plunify asks of ours. Yet, Mint is able to allay a lot of these concerns(not all--a fraction of consumers will most likely never be convinced).

At Plunify, instead of your bank passwords, what we ask for is your source code.
Which are just as important as your banking details.

One of the things that we like about the Cloud is how much more security we can provide to our users.

Plunify uses Amazon Web Services (AWS) for your Cloud resources. We spend a lot of time understanding AWS's security policies because this is important to our users.

To highlight a couple of important points of the 22 page security white paper.

1) Certifications and Accreditation
Amazon controls are evaluated every 6 months by an independent auditor in accordance with Statement on Auditing Standards No. 70 (SAS70) Type II audit procedures.

2) Employees
AWS requires that staff with potential access to customer data undergo an extensive Amazon Web Services background check (as permitted by law) commensurate with their position and level of access to data. Every access grant is reviewed every 90 days and explicit re-approval is required or access to the resource is automatically revoked. When an employee’s record is terminated, Windows and UNIX accounts are disabled and Amazon’s permission management system removes the user from all systems.

3) Physical Security
Datacenters are housed in nondescript facilities. Physical access is strictly controlled both at the perimeter and at building ingress points by professional security staff utilizing video surveillance, intrusion detection systems, and other electronic means. Authorized staff must pass two-factor authentication a minimum of two times to access datacenter floors.

4) Network Security
AWS Security regularly scans all Internet facing service endpoint IP addresses for vulnerabilities (these scans do not include customer instances).
Of course, there are protection against network attacks, firewalls, intrusion detection systems are in place.

And the list goes on.

Frankly, security in the Cloud seems better than that in most companies we know.
For those companies, their core businesses aren't about IT infrastructure so they tend not to invest so heavily into IT security, infrastructure and related personnel.

On the other hand, all it takes is for one AWS customer to report the leak of sensitive data as a result of using the AWS Cloud, and Amazon will be in deep trouble.

We hope this gives some assurance about cloud security. Although technology doesn't fully answer the security and trust questions, effective use of technology will go a long way to allay users' concerns.
In a second part on this topic, we will put up more information about how Plunify protects your data as well.

If you have any questions or comments, feel free to let us know.

有关FPGA设计的小贴士 - FPGA design tips (简体中文 followed by English)

2010-09-13T01:35:00.000-07:00

(Reproduced from eefocus.com)
Some tips on FPGA design found online, apparently contributed by an experienced designer.
Thought it made some good points with respect to general ways to approach the process.

很多人在学习FPGA设计，这里转载一个老鸟的博文，谈谈FPGA设计的17个小贴士。

1、状态机的问题，尽量不要写出太大的状态机，宁愿用一些小型的状态机来相互关联。

2、推荐大家使用timequest来做时序约束，好处是，它可能对你的时序约束和你的设计对照做分析，在做时序分析之前，先对你的约束做分析，然后告诉你，你有多少该做的事情而没有做的（为被约束的路径）还有多少你要求做的，而没有被做的（被忽略的时序要求）。

3、对时钟的约束，要重点关注两个现象。首先是尽量少的在时钟路径上引入逻辑，否则可能造成了时钟和时钟之间的skew。另外就是一种上下沿都需要用来采集数据的时钟。对于时钟的约束有很多的地方需要注意，否则你的电路都不知道会飞到哪里去。

4、约束中最重要的一个关键，不要过约束。过约束的坏处一大堆，增加编译时间，资源使用过度，导致其他的时序问题。如果你对自己的约束有些不太放心，又或者说可能器件和器件之间会有很细微的差别，你可以给约束做一些余量，但是过约束是万万要不得的。

5、 IP的作用就是为了完成一个特定的功能，所以我们并不需要知道它是如何实现的。作为一个IP，最重要的，其实是接口，因为你最重要的是需要知道是怎么让它工作起来，而不是它怎么工作的。所以在看文档的时候，最主要看的就是接口信号，对所有的信号的作用有一个了解。例如，NiosII CPU作为一个比较大型的模块，使用的是Avalon MM 点对点接口，它与普通的PCI接口不同的地方是，他可以支持同时多线控制。因为它没有总线的概念，不会在总线被占据的时候，其他任何通讯都无法进行。 NiosII是在SOPC builder 中被直接使用的，我们不需要知道具体有哪些信号，因为没有非常需要，我们是看不到这些接口的。在NiosII中，我们有两个Master Avalon MM 接口，一个是Instruction Master Port, 这是CPU用来读取指令的接口。CPU通过这个端口从Memory上读取指令。另一个是Data master port, 很简单，这是用来连接数据通道的。比如说你要读取的数据，你要存储的数据，都是走这个通道。这两个端口可以连接同一个内存，在这种时候需要特别小心，很有可能自己把自己的指令给改掉了。但是反过来思考一下，其实我们可以做什么？可以按照状况改变软件代码。NiosII中还有第三个端口，这是用来做 Debug用的端口。还有其他的一些接口，比如TCM接口。我们需要知道这些接口的存在，但是不需要知道细节，只有在用到的时候再去看相关的文档就好了。

6、作为系统设计，是需要有一种粗旷型的大气魄，不需要在细节上浪费时间。你会发现很多的细节是没有意义的。并不是说我们不需要去研究细节，细节是很重要的，但是细节需要在被用到的时候才去关注就好了。

7、在使用IP的时候，会遭遇到意想不到的痛苦的。所以，尽量不要依靠假设来臆想了模块的设置。而是尽量的适应环境，来配置自己的设计。作为一个FPGA的玩家，这种依照环境来改变的能力是必须的。

8、考虑Cashes的设置，Cash 有两种，一种是用来做指令缓存的，一种是用来做数据缓存的。Cash的大小对程序的运行速度是有影响的。当然也没必要使用过多的资源。够用就好了。

9、自定义指令设置。这是最有价值的设置。所谓自定义指令，并不是一个软件宏或者函数。而是一块硬件。当CPU调用到这个指令的时候，事实上它调用的就是这个硬件模块，它被嵌入在CPU中。而这其实就是NiosII好玩的地方。

10、SOPC builder是QuartusII中用来建立，开发，维护系统的平台。虽然很多时候我们用它作为NiosII的一个嵌入式系统的开发环境，但我不要把思路只是局限在NiosII上面。它将成为一个包容全部系统内容的一个平台。

11、 Avalon接口分成两种，一种是Avalon-MM接口，另一种是Avalon-ST 接口。MM接口，是通过地址来读写数据，更多的是用在控制逻辑上面。ST接口是用于点到点的流数据接口，更多的可以用在有高速通过率的模块中间。这两个接口本身并没有矛盾，不是说势不两立的，一个模块中既可以有MM接口，甚至几个MM接口，也可以同时存在ST接口。作为一个点对点的接口定义，Avalon 可以做到高效的接口效果。这与PCI之类的总线接口是有本质区别的。PCI总线可以看作是铁路轨道，当一个火车在轨道上行驶的时候，就不可以有另一个火车同时使用轨道。Avalon接口更多好像高速公路，车辆可以双向行驶。

12、作为FPGA设计中比较独特的一个原则就是，这个世界不是你创造的，所以你必须去适应它，而不是顽固自己的意图。

13、在FPGA中，除了门与门之间的延迟是固定的（时钟频率）外，一切的组合电路的延迟都是不确定的。记住这样一个规律就好了，凡是没有被门关过的信号都是不稳定的，都只是暂时的。

14、在生成新的再生门（一些逻辑的结果作为时钟去驱动一个门，我们且管他叫作再生门吧）之前，你最好把这个时钟信号用原来的那种门在关一下。这样你获得的会是一个干净的，纯粹的时钟信号。

15、针对新的一些器件，器件本身可以提供一些时钟控制模块，当你需要使用门锁（gated lock）的时候，尽量的使用这些模块，会让你的时钟变得安全（clock control block）。

16、如果你不得不使用逻辑电路来锁门，而你的器件又没有特定的模块。那么最好的情况就是，你可以先用那个时钟，把你的门锁信号关一下。这样的好处就是可以把毛刺信号完全的规避在门外面，使你的时钟更加安全。

17、上电初始值
在通常的状况下，所有的门在上电的时候输出为低。但是这并不是不能改变的。你可以把上电设置为高，这样综合工具可能会做两种事情，把输出反向，或者使用preset控制（如果存在的话）把初始值放进门里。
当时上电为高的做法，并不是非常必要，因为你其实是可以使用复位信号来获得你想要的初始状态的。

Many people are learning FPGA design, and here are some tips from an old hand.

1、Try not to have large state machines, but rather smaller ones that communicate with one another.

2、 It is recommended that Timequest is used to create timing constraints. The benefit is, before it analyzes your timing, it will first analyze your constraints and then inform you about unconstrained paths and timing requirements that you haven't attended to.

3、 Two things are worth noting with regards to clock constraints. First, as much as possible avoid inserting logic into the clock path, otherwise clock-to-clock skew may occur. Second, be very careful when gathering data on both edges of a clock, otherwise your circuit might well end up in lalaland.

4、 The most critical point in constraining is not to over-constrain. There are many pitfalls of doing so--increased compile time, utilizing more chip resources than necessary, all resulting in other timing problems. If you're concerned about your constraints, or if there are minute differences in timing characteristics from device to device, try giving more allowance in your constraints, but never over-constrain.

5、 The purpose of IP is to fulfill a specific function, so we don't have to know how a particular piece of IP works. The most important aspect of an IP core is its interface because that's all you need to make it work for you. Hence the most important section of an IP core datasheet is its interface chapter.

For example, Altera's NIOS-II CPU is a somewhat large module which uses an Avalon MM point-to-point interface. It differs from a "normal" PCI interface in that it is a simultaneous multi-master interface.

The NIOS-II is directly invoked and used within the SOPC Builder software. We don't need to know what signals it contains, for we won't be able to see those internal interfaces unless there is a real need to do so. In the NIOS-II, we have two Master Avalon MM interfaces, one of which is an Instruction Master Port--used by the CPU to fetch instructions from memory.

The other is the Data Master Port; simply put, this is used to connect datapaths. For instance the data you'd like to read and the data you'd like to save both use this datapath.
These two ports can be linked to the same internal storage. However, in that situation great care must be taken to avoid overwriting your own instructions. But thinking about it, what can we do with such an implementation? We can change our software code depending on the situation.

NIOS-II has a third port that is used for Debug, plus some other interfaces like the ITCM. We need to know that those interfaces exist but we don't need to know the details until we actually use them. When that time comes, we just need to consult the datasheet.

6、 A system designer needs to be bold and daring, and not waste time on details. You will find that many details are meaningless. This is not saying that we don't have to look into the details; details are very important, but they need to be given attention only when they are utilized.

7、 The use of IP brings with it many unpredictable issues and pain. Hence, as much as possible, don't rely on assumptions to guess a module's setup. Instead, adapt to the situation in order to deploy one's own design. This kind of improvisation is essential for an FPGA user.

8、 Consider the cache configuration. There are two types of caches--instruction caches and data caches. Their size affect software execution speed. But there's also no need to use too many resources for caches. Just enough will do.

9、 Configuring custom, user-defined instructions. This is the most valuable type of setup. A user-defined instruction in this case does not refer to a software macro or function, but to a piece of hardware. When the CPU invokes this instruction, it is invoking a hardware module which in embedded in the CPU. That's the fun of NIOS-II.

10、 SOPC Builder is a platform within Quartus-II that's used to build, develop and maintain systems. Even though we often use it as a development environment for a NIOS-II embedded system, let's not limit our thoughts about it to just a NIOS-II platform, but rather as a platform for an entire system.

11、 There are two kinds of Avalon interfaces, Avalon-MM and Avalon-ST. The former is used to read/write data via addresses and is more used for controlling logic. The latter is for point-to-point streaming data, more for use inside high-speed filter modules. These two interfaces aren't contradicting or mutually exclusive, and can co-exist in the same module. There can even be multiple MM interfaces. As a point-to-point interface, the Avalon interface can achieve high throughput. It is fundamentally different from a PCI interface; think of a PCI interface as a railway track--only one train can travel on it at a time. An Avalon interface is like a highway--multiple cars can travel on it in two different directions.

12、 A rather special principle of FPGA design is that the world wasn't made by you, so you must adapt to circumstances and not stubbornly stick to your own intentions.

13、 In an FPGA, apart from gate-to-gate delays which are fixed(clock frequency), all other combinational circuit delays are uncertain. Just remember this rule: all signals that aren't gated are unstable and temporary.

14、 Before generating a gated clock(using the result of some logic as a clock to drive a gate), you'd better use the same primary clock signal as an input to the gate that generates the gated clock signal. This way, you get a clean clock signal.

15、 Newer devices have embedded clock control modules. When you need to use gated locks, try to use those modules as much as possible. That will allow your clock to become stable.

16、 If you have no choice but to use a logic circuit to lock a gate and your device doesn't have specialized modules, then the best thing to do is to use that clock to gate your gated lock signal. That way, glitches are prevented and your clock becomes more stable.

17、 Under normal conditions, the initial output values of gates at power-up are low. But those can be changed. You can configure power-up values to be high. This kind of integrated tool can do two things--either reverse the output or use some sort of preset control (if it exists) to configure the gate with the desired initial value.

This is not really necessary because you can actually use reset signals to get the initial conditions that you want. If you really have to, there are several ways to do it... (the rest is cut off)

Sigasi - a breath of fresh air for VHDL designers

2010-08-25T08:02:00.000-07:00

A few months back I began noticing ads in my email window about a tool for VHDL design called, "Sigasi HDT". Being a hardware developer, I was naturally intrigued and looked at their website. The picture on the landing page soon had me chuckling, and as I read about Sigasi HDT and the philosophy behind it, I realized how apt it was to show a caveman staring in wondrous surprise at a computer screen.

Programmers in the software industry generally have it better than hardware designers in terms of development IDEs, wouldn't you agree? The GUIs are easier to use and have features that have more to do with the actual code under development rather than just syntax highlighting. For example, tracing a variable in all its incarnations throughout a software project is made a lot easier with some of the better IDEs out there. Some help to simple avoid making common errors would be a boon.

In the hardware world, I haven't heard of any IDE like that. Until Sigasi HDT came along, that is. In Sigasi's words, "It differs from other development tools in that it contains an ultra-fast VHDL parser and compiler that runs transparently in the background." There seems to be many features of note with refactoring a highlight. Refactoring, in my crudely-expressed terms, means cleaning up code, making it shorter and better.

I'll be looking to dive into Sigasi HDT a little more, but it seems like the Sigasi folks understand the little details that would make life easier for hardware designers. In terms of logistics they have Sigasi HDT in the form of an Eclipse plugin so that it's easier for people to install Sigasi HDT into their current design environment. (We hope there will be a web version too, in future!)

Through a series of Tweets and blogs, Kirvy and I had the pleasure of connecting and eventually speaking with Philippe, one of Sigasi's founders. We exchanged ideas and talked a little about the visions for our respective companies. It was nice to learn that they are now offering free educational licenses to academia.

It's a breath of fresh air to see products like this.

How green is cloud computing?

2010-08-21T22:28:00.000-07:00

One of the benefits touted by Cloud Computing advocates is that besides monetary gains through economies of scale, there are also benefits for the environment.

Came across an article by Reuven Cohen, a cloud computing evangelist, that tries to quantify just how green the cloud is. Data seems hard to obtain at this moment, it seems.

One interesting anecdote is that apparently a city in Finland uses generated energy from data centers to heat homes.

Intuitively there's a ring of truth but it's so very important to have numbers to back it up.
James Urquhart, a CNET columnist, commented on Cohen's article with some optimism.

"So, in a sense, the 'greenness' of cloud computing is a kind of Schroedinger's box problem today, in which we won't know the actual savings to the environment until someone actually observes--or measures--it," he remarked.

It would be great if Amazon or another cloud provider publishes a bit of data.

Raison d'être

2010-08-17T03:12:00.000-07:00

We were asked recently by investors, users and fellow community members questions that prompted some reflecting upon where Plunify is now, and where we are heading. Perhaps surprisingly, Kirvy and I haven't deviated much from those drawn-on-a-napkin plans that we concocted way back then. The napkins have long since disintegrated but the dream remains.

Plunify is a startup in the FPGA ecosystem.

Our project came about because there seemed to be too many disjointed steps for creating a working FPGA design.
The situation is still pretty true today.
IP, tools, compute resources, testing, debugging, optimization, evaluating devices, etc. make it hard for users to concentrate only on their designs. A couple of specific problems include:
- too much time is spent on synthesis, place-and-route iterations
- it is a hassle to install, maintain software and PC/server hardware
- it is not easy to compare devices across FPGA vendors
Not only are gaps present in technical areas such as benchmarking, business information like device prices and availability are often hard to come by.

Plunify is an attempt to link these pieces up and to make programmable logic design as simple as possible. In a way, our vision is to become the "Salesforce for FPGA design".
We are making an all-in-one platform to solve these problems, but as you know, small startups have to prioritize ; )
For a start, the focus is on using Cloud Computing to enable basic, online FPGA design capabilities.
Besides providing a platform that abstracts unnecessary details away from users, the cloud infrastructure also helps to speed up synthesis, place-and-route to often significant extents.
In addition, the cloud enables us to adopt a vendor-agnostic interface so that users, especially new-comers to FPGA design, won't have such steep learning curves.

Currently Plunify's beta platform supports Altera and Xilinx. Two Open Source simulators, Icarus Verilog and GHDL, are also available for simulation.
Through a web interface, anyone can implement FPGA designs in the form of Verilog, VHDL, netlists and constraints files.
Subsequently, users can compare results across different devices like this example which was done for an Open Source processor core.
Through carefully allocating Cloud Computing resources, we found that up to 75% of implementation time can be saved in some cases!

User feedback has been quite rewarding so far.
Just today, a group of students who weren't familiar about FPGA design apart from simulation, and who have no FPGA tools installed on their PCs managed to use http://www.plunify.com to create a working FPGA design within an hour!
What's really cool was that they managed to do this far from their engineering lab, and relied only on a USB modem throughout!

Going forward, we are working hard to add features based on user feedback, and hope to get more traction. In particular, we'd like to automate things like constraints testing, which are currently both tedious and perhaps not so straightforward to figure out.

Ultimately, we hope to contribute towards a more open FPGA community and simplify the use of FPGAs all over the world!

New to FPGAs / logic simulation?

2010-07-08T22:33:00.000-07:00

A Brief Plunify Simulation Tutorial

The following step-by-step guide to simulation is aimed at users new to Plunify or to FPGA design in general.

After a design is described in Verilog / VHDL, usually the next step is to run a simulation in order to verify if the general functionality is correct. There are many types of simulations and simulators.

Plunify can be used to simulate a Verilog / VHDL design, using the Icarus Verilog and GHDL simulators. The following example uses a simple counter in Verilog, provided by default when you register with us.

First, log on at www.plunify.com.

The Project Manager's initial page appears.

Your home directory and its contents are displayed on the left.

Click and navigate to /Home/Sample_Project/Simulation/Verilog/counter/

Click the "Simulate" tab.

Select "Verilog (Icarus Verilog) as your simulator.

Select your Verilog source files using the built-in file explorer.

Click "Next".

Click the "Simulate" button.

(In this case, we don't have to specify a "Commandfile", which is a batch file that Icarus Verilog uses.)

At this point, your simulation has started.

Click "Close", followed by the "Reports" tab.

Your simulation will be displayed under "Pending Jobs".

When the simulation completes, its job entry vanishes from "Pending Jobs" and appear in "Completed Jobs".

A blue notification message also pops out near the top.

To view results, click the above message (You will also be sent a notification email).

Click "View" beside your job entry in "Completed Jobs"

Two, potentially three types of results exist:

Compilation
Run, and
Waveform (if enabled in source files)

Click "View" beside each result to examine them. These files can also be downloaded.

To view a simulation waveform, click beside the waveform file.

The built-in waveform viewer pops up in a new tab / window.

Display relevant signals by selecting them and clicking the "Display Waveform" button.

Use the scroll and zoom buttons to examine your waveform and debug your simulation.

But of course, simulation is a repetitive process, at least until your design works.

Make changes to your source files and upload them.

Run the simulation again via the above steps, or use the button.

This concludes our brief simulation tutorial.

Feel free to try the other examples as well, which include the same Verilog counter but with an Icarus Verilog command file, and a VHDL adder example that uses the GHDL simulator.

Questions / comments / kudos / hate mail can be sent to tellus@plunify.com

From DSPs in FPGAs to overall trends in the FPGA world

2010-06-30T19:02:00.001-07:00

Came across an interesting discussion on a LinkedIn group regarding first, DSPs in FPGAs, followed by observations on trends for future FPGAs.
Highlights:

How to accelerate DSP applications in FPGAs so that ASIC implementations will fall behind
Custom blocks in FPGAs and how they are positioned to capture more designs
Motivations of FPGA makers for putting certain architectural features in future devices

One poster mentioned that FPGA makers are not so keen on promoting embedded blocks in FPGAs because doing so devalues the programmable side of the technology--the FPGA fabric.

The Growing Tide: Hardware Design in the Cloud

2010-06-24T04:29:00.000-07:00

We feel like surfers in an hitherto undiscovered surfing paradise, believing that the big waves(FPGA Design in the Cloud) will come and working hard in preparation (developing Plunify's platform) for them. When the waves come, we just have to time it right, paddle like crazy and stay in the sweet spot.
But we have to create conditions for the waves to come as well.

Our success depends on it.

Luckily since we started working on Plunify, we could feel the waves coming, and they might well form a tsunami.

News from the recent 47th Design Automation Conference(DAC): Even the EDA world is looking to the cloud for solutions

The cloud is not new, of course. It's merely a more mature form of the server farms of yore.

What's different is how companies, especially startups like us, are springing up to provide applications as services.

A few main obstacles to user adoption have been identified; here they are (Source: EETimes) and here's how we are solving these issues for the FPGA world:

Will the design be stored locally or at the vendor's site?

Trust involves both human and technical factors. On the technical side, we encrypt transmissions and set strict user permissions on data stored on our servers. We even delete source files after we're done processing.

But that's not enough, is it?

We let clients store source files locally on their PCs, and just access the tools remotely. Speed and scalability are tradeoffs in that case, but IP security is assured.
How does the application handle authorized--and unauthorized--access to the design?

Protection occurs at several levels: the OS, the filesystem and at the web frontend, in the form of passwords, SSH and SSL authentication.

A friend who works in the military doing IT security is coming over to hack into our system. We shudder at the holes he is going to uncover, but are looking forward to patching them up!
How often will tools be updated, and will users receive enough advance notice?

This is an issue that bugs many FPGA designs--namely the tool version changes and a working design breaks.

We keep all supported versions available and track which designs work on which tool versions, so users should never get into that situation with Plunify.
Does the hosting provider have enough bandwidth to support very large files?

Bandwidth was part of the reason why we use Amazon AWS as our cloud provider.

To be honest, we haven't really felt any bandwidth pressure yet. The system seems to be handling itself quite nicely.

Things are slightly different between FPGA and IC design, even though processes are similar.

It is great to hear that the industry is responding favorably to what we're doing. But the proof of the pudding still lies in the eating--how users feel about our solutions to the problems above. Or will we uncover new user concerns?

That's part of the fun, and the challenges.

OK, back to work.

How important is the time taken for synthesis, place-and-route?

2010-05-20T14:40:00.000-07:00

Recently, one of us posted a question on a discussion forum about how important synthesis, place-and-route time to developers?

There were quite a few responses; most people agreed that as FPGAs and FPGA designs get more and more complex, implementation time becomes a larger portion of the development budget or project timeline.

As silicon process technology gets smaller, increasing the number of gates the software tools have to route for FPGAs, makers also add more complex blocks in the FPGAs. As FPGAs become more complex, the time spent to design, implement and debug increases. One needs more iterations to complete a design--hence how fast the tools crunch one's design directly affects when the design will be completed.

Some respondents said that there are just too many other variables that are equally important.
Which we take to mean, there are many areas for improvement in the FPGA world!

Others proposed a higher-level view: that we should take a step back and focus on improving design methodology instead.
That's where more gains could potentially be made.

Full discussion on LinkedIn.

What do you think?

Starting an FPGA design

2010-04-21T21:09:00.001-07:00

There are certainly many ways to start an FPGA design; for example one can:

Open up an editor and start coding
Look for, duplicate and modify an existing reference design

Which approach one chooses is probably a question of deadlines and personal preference.

Our engineers, for example, learned to design by coding so if given the time, they would rather write it out in Verilog/VHDL while referring to reference designs if any exist.

Coding something at least once and making that work is likely the most effective way of "learning by doing" in our opinion. Should you be blessed with the luxury of time and curiosity, there are plenty of resources out there to help.

First, pick a language from the current de-facto standards: Verilog or VHDL. References abound for these two languages and they have been in active use for decades. It seems that VHDL is more popular in Europe and in military/aerospace applications. Verilog accounts for the most of the "rest".

SystemVerilog and SystemC have been on the fringes for a while now, and are seeing increasing use. However their adoption seems to be hampered by a lack of robust and readily-available tool support.

Important things to look out for while coding include:

Sequential(anything that remembers state) and Combinational logic
Blocking vs Non-blocking statements (see quick explanation)
Clocking--see here for a discussion on differences in clock-gating between ASICs and FPGAs

Having an already working reference is a boon in almost all(except when the reference design is too convoluted to understand!) cases. Finding a suitable one might involve trawling FPGA vendors' and design services' and tool vendors' websites for "application notes" or using specialized search engines.

Once a suitable one that fulfills one's end-application is found, here are some considerations:

Is it available in source code or at least, can it be easily modified?
What application software/hardware is required to test it - boards, drivers, end-applications?
Which software/hardware tools are needed to run it and produce the same outputs as advertised - FPGA tools, simulators?

The above factors likely dictate if this reference design is going to be useful, impossible to replicate or too limiting.

Whether the design is created from scratch or from an existing reference, the typical steps in the development process are:

Functional simulation to prove that your logic works(no going into timing yet!)

Shameless plug: Our online simulation platform using industry-grade simulation tools can help you do functional simulations with minimal hassle!
If functional simulation passes, time to implement your design on FPGA software

Input constraints such as clock frequencies and pin locations so that the FPGA software can try to compile your design for your desired speed and IO(e.g. connect the Write-Enable in your code module to the physical Write-Enable signal on your eventual hardware test board) behavior.

Here is where one gets intimately familiar with the FPGA software :)
Typically one also picks a specific FPGA/CPLD device here--which always seems strange because at this stage it is too early to commit to a specific device in our opinion. Kinda like limiting yourself to one tree before understanding the entire forest of possibilities.

Run the FPGA software to put your design through synthesis, place-and-route, timing analysis and finally(if all goes well), programming file generation.
If failures occur,

Examine error logs
Can't meet target frequency? Too long a datapath? Software can't wrap its head around a certain code construct? -> Change source code
Constraints are too strict? -> Reduce target frequency or move IO pins or relocate logic blocks

Repeat

If at the end, you get a working design, all the above was worth your efforts!

Open source FPGAs?

2010-04-04T09:31:00.000-07:00

The phrase, "reconfigurable computing," seems to bring to mind flexibility and freedom of choice.
It seems natural that some of this flexibility should mean that developers will have all the information to target whichever programmable logic device that is best for their designs.

In the FPGA world, since understanding the structure and format of bitstreams and how they are formed could mean exposing intimate details of the device to the world, from a chip manufacturer's point of view, divulging less is understandably more desirable.

Unfortunately it also means less people can work on improving software tools for implementation--map, floorplanning, place-and-route, bitstream generation.
There are few open standards for apples-to-apples comparisons as well.

It is almost like the software industry of the 1960s-70s, when big companies dominated the scene with proprietary formats and tools.
- Compilers were hard to write then, but they became easier and eventually standard, open source ones like the GNU C Compiler came along
- Software was mostly written in-house and few believed it could be out-sourced
- Personal Computers and sharing of IP were almost unheard of

One could argue if the software industry has evolved for the better or for worse since then, but I certainly enjoy being able to write a program on my laptop, compile it and run it right away without so much as a simple installation of Linux and gcc. Come to think of it, Linux would probably have not become what it is today.

Perhaps one day every piece of electronics would really have a generic programmable logic device and one could just write a program to run on it without having to download and install proprietary tools, search too hard for suitable IP(More of sites like http://www.opencores.org and http://www.rmdir.de/~michael/xilinx/ please) and learn too many different tool interfaces.

Without going too much into the merits and demerits of open source software / hardware, I tend to think that going down the path of open sourcing FPGA architecture and software would lead to greater engineering benefits. For business reasons, more clarity may not be a good thing perhaps, or at least business models would have to be tweaked for many companies who are used to the current models in the FPGA industry.

How not to be crushed like an ant

2010-03-15T10:13:00.000-07:00

Comments from VCs and senior industry people whom we've talked to resonate constantly in our minds. Especially those which express concern over how we're going to sell our simulation and PLD-matching services.

For example, our goal of providing accurate technical information to simplify the process of FPGA/CPLD selection for any design might not sound too pleasing to chip manufacturers, because heck, sellers may want to sell the highest-margin products, not necessarily the ones that suit customers best. From a business perspective, this is only natural.

But from the perspective of helping manufacturers sell chips by making programmable logic design easier, we think we're providing value to both PLD makers and users alike. Guess it depends on who you talk to. Looking at examples in the PC and automotive industry, it does seem like having more information spurs innovation and choices, resulting in higher efficiencies for everyone.

Of course, it is rather premature to be talking about annoying chip makers when our product is not even close to launch! However, it does have implications on how we market and sell. For example, various sales channels exist for PL design services and tools. We could perhaps bundle our services with a larger company's distribution channels and be part of a more complete package of, say, boards, test equipment, etc. That will immediately grant us a large number of customer leads. If our partners think that our services will lead to lower sales for any of their products, our unions won't last very long, would it? :)

Beta-testing, (another) New Year, starting work on Onsen

2010-02-15T16:49:00.000-08:00

Another round of holidays is upon us--today being the 2nd day of the Chinese New Year, a super long weekend in Singapore.

With little distinction of working days versus rest-days, we plod along as usual.

On the simulation side of things, we have been extremely blessed with expert beta-testers--friends and former colleagues who have devoted their free time to breaking our simulation platform. In the beginning, it was like slicing a hot knife through butter. (Despite our best efforts, nothing beats having a user to test one's code) After a couple of "Oh..." moments, the system is taking shape nicely.

Now we say with greater confidence that you should be able to log in, upload your HDL code, and run a simulation successfully. At no charge, of course.

Next, our online "Match-your-design-with-a-PLD" attempt; As of now, we have several hundred FPGAs and CPLDs in our servers, crunching happily on small designs that we downloaded off the web. Some tests error out quickly because of parameters that we neglected, whereas some run to completion successfully. It is too premature to be of interest--not even alpha, but things look encouraging.

Very happy with the new office

2010-01-15T02:41:00.000-08:00

Amidst a flurry of New Year celebrations, we moved into our new home in Bugis, an area known in the 1950s-80s for transgenders as well as for ethnic shopping. Nowadays, it's a hodge-podge of office buildings, shopping malls and eateries.

Compared to our previous office, the new one is light-years ahead in terms of furniture and facilities. Location-wise, it's also very convenient as no transfers are needed.

Each of us has a big table and extremely comfortable chairs--compliments of our landlord so we're happy. The upcoming weeks will still be spent in development and naturally, exploring the surrounding eateries ;)

Feature-wise, we're just getting into stride with the online simulation and will resume work on the automated FPGA implementation next week.

Merry Christmas and Happy 2010!

2009-12-23T19:32:00.000-08:00

To our families, friends: A big thank you for your support and encouragement!
To other entrepreneurs: All the best and may all our endeavors bear fruit!
To everyone: Merry Christmas and Happy New Year!

Office space

2009-11-15T22:41:00.000-08:00

We had the good fortune of having an office before we registered Plunify--thanks to one of the founders who was already running his own setup. So the rest of the folks just pulled up extra chairs to his existing table and hit the ground running.

The building: a remodeled pre-war (the 2nd) police barracks with no elevators, dingy bathrooms and steep, narrow stairs. But the location was superb--smack in the middle of bustling Chinatown with convenient access to everywhere else.

No bugs (creepy crawlies) or hauntings (although huge buddha statues rest in one of the side stairwells) but the rent was a bit steep (~$3/sq ft) and when there's a thunderstorm, power failures are more common than not. 24/7 access works out great for all of us. One other funny thing is that our Singtel business line would go out at least a few times a month, often around 4pm. We speculate that either someone was tapping our connection or perhaps Singtel changes IP addresses at that time and our aged modem can't handle it.

Anyway, the time came when the shared office started feeling too cramped, so we embarked on a search for a new home.

Why do you guys not work from someone's home or separately, you might ask; well, here's our take:

Pros of working together in the same room:
- Working physically next to one another
- Keeps work away from home
- Psychologically
- Logistically
Some elements of software agility support our preferences too.

Cons:
- Rental expenses

Criteria for the new office:
Location:
- Convenient for employees with cars and those without
- MRT, buses
In tropical weather, walking more than 10 minutes to get to the office often means a choice between being drenched in perspiration or in rain. Good thing nobody has to wear a suit to work!
- Proximity to customers
- Good thing local customers are very accessible due to both the size of Singapore and her efficient transportation network
- Most customers are abroad so all it takes is an air-ticket and some advance arrangements

After a couple of days of looking around and answering ads, we shortlisted a couple of options, but were not 100% happy with all of them.
- cheapest one of all--a room on the 2nd floor of an old shophouse; no natural light, old carpeting, not very appealing
- next in terms of decreasing affordability--an office in an industrial complex; inconvenient to get to, need to buy furniture
- next, a service office close to the city center--no natural light, space was smaller than advertised

In the end, something came out of the blue. We're still pinching ourselves on this one. A couple of kind entrepreneurs we chanced across generously offered us very affordable office space complete with facilities and use of office equipment!

Needless to say, we thankfully accepted and now we look forward to moving to the new place on Jan 4th. May 2010 get better and better!

Meeting with prospects

2009-11-02T01:07:00.001-08:00

Last week we had an initial meeting with a customer--details are hush-hush at this point of course but suffice to say they have impressive educational/research facilities. They kindly bought us lunch in an opulent banquet room although I have to say that both of us were too busy listening and making sure that pieces of food were not stuck in our teeth while we were talking, to really enjoy the food! Pity, really, because it was a sumptuous spread.

After the pleasantries, we explained who we are, what we do and gave a demo of the current simulation platform--a canned demo where Verilog source code for a simple counter was compiled via our web interface and server, and then the resultant waveform files debugged via the web browser as well. Our audience seemed reasonably pleased and asked for more details, which was very encouraging for us to say the least.

The questions we received included:
- Does your tool have the same feature-set as the tools from C and S (major industry players)
- How can we provide a complete learning experience for our users?
- Will our IT staff be able to integrate your platform with relative ease?
...
etc.

It may sound silly, but from the meeting and from subsequent discussions with other prospects, I started to get a feel for the dynamics at a customer's site. Besides identifying the right people to pitch to, and cultivating the ability to sincerely listen, I realized that I have to put each different individual's reaction and requests in the context of their roles in the customer's organization. For example, a relatively junior engineer is likely to care more about the ease of use rather than how a solution scales. A person who works within the boundaries of his/her job description is likely to be receptive only to points that fall within that description and not to "How can things be improved beyond the scope"-type of suggestions.

With these in mind, we're preparing proposals for the next round of interaction. It may be a slow process but already it is pretty rewarding!

Of course, at a demo, be sure to check with the coordinators if they have the necessary equipment. For us, fortunately we had everything so all we needed was a wireless network connection. Thank goodness for the free (as in $0) Wireless@SG!

All these would not have been possible without YC's kind introduction to the powers-that-be, of course. Thanks again, YC!

Incorporating in Singapore

2009-09-14T18:34:00.000-07:00

Previously we went through the necessary step of making Plunify a legal business entity--a process which was fortunately relatively painless.

In Singapore, it seems fairly straightforward to get one's business registered, at least compared to Tokyo and the San Francisco Bay Area. The fees are comparatively lower as well.

First, one surfs over to the ACRA website at http://www.acra.gov.sg
The Accounting and Corporate Regulatory Authority of Singapore seems pretty new-business-friendly and has set it up such that most procedures can be done online.

Figuring out what to do exactly, however, can be non-trivial depending on the type of business entity one is registering. For example, sole proprietorships and limited partnerships are relatively simple. A corporation, or what is known as a private limited company, involves more brain cells.

Interesting (to me) distinctions are made between a "business"(sole proprietorship / partnership) and a "company"; full details can be found in the Companies' Act.

Plunify falls under a private limited company because, among other things, we would like to register property and capital assets required for our business in Plunify's name. After making sure that we satisfy the eligibility requirements, we then made the decision to let a specialist vendor handle the incorporation for us. That involves things like setting up bank accounts, hiring a corporate secretary to file our annual accounts with the regulatory bodies and putting into writing things like share ownership and who gets to take the office chairs home if the business folds. Our vendor? Just google something like "incorporation services singapore" and there will be tons of relevant hits. We just called each one in turn and decided on one which felt the most comfy. Cost and professionalism were our deciding factors. The government also provides one called The DP Bureau.

Little details, but essential to get the business going. Of course one can do it without enlisting any help. For us, it was a matter of asking that same old question, "Is our time worth the amount we're paying the vendor?" again.

Harnhua

Learning by doing

2009-08-26T17:06:00.000-07:00

The past month was a very satisfying one in term of workflow. Finally we've managed to devote more time in terms of full days (and nights) to Plunify. Finally many other commitments have been fulfilled, freeing up precious time.

This post is a bit fuzzy in that I just wanted to summarize a few things we've reflected upon in the last few weeks:

Nudging the flywheel
Jim Collins in his wonderful book, Good to Great, mentions the importance of working incessantly on little things that make up one's overall goal. Eventually (hopefully) every little ounce of preparation builds up enough momentum to propel your startup/organization forward.
I feel that this train of thought is not just about leaving no stone unturned but also about gauging the relevance of tasks that we are working on. It sounds obvious, but before doing most things, we've come to ask why we're doing them and how they can help our overall goals. For example, building a business relationship with distributor X to sell FPGA design guides or writing a script to automate file transfers across servers. Since time for a startup is precious(gotta make $ before the $ runs out!), we really have to evaluate what we do.
Interestingly once such questions are asked, we usually get a gut feeling of what's "right" and "wrong". And it really helps focus us on the "right" tasks, not to mention deepens the sense of satisfaction when such tasks are completed.
Of course no one can predict the implications of every task. Discussing it within the team and with outsiders should help determine its relevance in the overall scheme of things. If it seems right after a good night's sleep, just do it and add momentum to your flywheel. Plunify's is only just starting feel its molecules stirring.
Sometimes the Wheel weaves as the Wheel wills ;)

Learning by doing
While getting from Step 1 to Step 2, inevitably Steps 1.001, 1.002 pop up in-between. Whether it is inadequate planning or just the way things are at the beginning, I don't know. But it certainly spices up the day! We could be coding a feature to remotely access a server and suddenly find that the PHP library we're using requires some tweaking. That tweaking might lead to more Googling which in turn causes us to download a compiler to re-compile changes to the PHP library.
The point is, we'd have never realized the existence of these extra steps without getting our feet wet. So to anyone who might be hesitant about venturing out on a limb: just take the first couple of steps and you'll find out the potential of your idea, quicker than most forms of advance planning and forecasting.

Engineers without borders
Working with people over the world automatically broadens one's perspective. From the start, we wanted Plunify to support multiple languages and to sell to customers. Hence every webpage has to have a corresponding Chinese or Japanese version. It's been fun asking friends if they are interested in translating pages for us. Does anyone know how to properly translate, "FPGAs are the predominant devices used in Programmable Logic Design today" into Chinese or Japanese for us? :)
The energy of the FPGA community is also nothing short of amazing. For example, no matter where we ask, people always have comments and ideas on how FPGAs can be made simpler for users. A potential board member could be emailing us from Indonesia while we're Skype-ing with an advisor in Japan. Is this the power of the "community" that people always talk about?

Harnhua

"F words"

2009-07-15T02:23:00.000-07:00

Much of what we're occupied with recently can be summarized by a few 'F' words, although not the ones that one might imagine ;) This phase of Plunify's progress might be termed the "sweat-and-blood" phase or simply, Product Development.

By the way, serendipitously, another 'F'--a Facebook widget was installed on our landing page www.plunify.com in a bid to engage users. Do check us out!

Features: Going through the list of things to do in order to start an FPGA/CPLD design, and coding them one by one into Plunify.
Feedback: Asking friends to try them out and then give us honest comments. Repeat.
FPGAs: Constantly thinking about Plunify's raison d'e^tre--making FPGAs/CPLDs/any type of PLD easier to use.
Funding: Cash flow and cash burn rate are always at the back of our minds, prompting the questions, "Can we get more funding?", "What milestone should we reach before applying for more?", "Who are the good incubators/investors out there?" etc.

First, the Feature we've been working on the past month is a reference design/board search function. It directly relates to one of the first steps taken when starting an FPGA project--look for an existing working example.
Targeted at both basic and experienced users, you can either type in keywords, for example "USB", into a typical search textbox or use an Advanced Search page to methodically check the board interfaces or reference design capabilities that you want.
Once you find what you want, intuitively one would wonder--how much of the FPGA's/CPLD's resources does this design consume?
Clicking on the search result, if we have data for it, you should see:

The yummy-looking cookies show a breakdown of the main resources consumed: logic elements, storage elements and IO. To the right, one can compare this design with others in the same set of search results.
Clicking on "Top 5 Results Comparisons" brings up:

And we're working on user-specified, targeted comparisons.
For the gory details, the Details tab also provides something like this:

Our data? Mainly reference designs and development kit information from Xilinx and Altera at the moment, but we aim to include as many reference designs as possible--from other FPGA vendors, distributors, design houses and individuals. For instance, a contributor on OpenCores.org can also list his/her design on Plunify. Contact us if you'd like to post your design.

A reference design will not fly with users if it is not verified in hardware/simulation, has little/no documentation. Support is also vital, especially for complicated designs or if documentation is not sufficient to reproduce the promised behavior. Therefore, for each design in Plunify, we inform you if the design has been verified or not, what you need to reproduce the results, and how much it is likely to cost you to obtain all the necessary pieces.

Gathering and entering the required data is an interesting and tedious task. Different vendors convey information in different formats/locations so sometimes it is difficult to sieve out the required bits. Oh, how I long for a "Reference design crawler"
(*scribbles on Todo list*) But when a user mentions that this feature is helpful, my my, the satisfaction is indescribable.

That brings us to Feedback.
After every alpha feature release, we have been asking friends from all over--the Valley, China, Japan to try it out and to critique. The Search feature is no exception. Since we also made changes to Plunify's website, Sean, Mary, Henry and 小澤さん were kind enough to comment on the entire site in general. I cannot tell you how helpful their feedback has been. Besides directly influencing what we do and
helping us improve, psychologically it motivates us to try harder to please. Simple as it sounds, user feedback are really the bee's knees.

The other two Fs: FPGAs and Funding
小澤さん and Henry raised some points about where Plunify is going, for example, how are users going to trust a company in its infancy like Plunify and will listing reference designs conflict with Plunify's goal of unbiased, transparent use of FPGA/CPLD/PLDs. Very good food for thought, and amidst much discussion, we realized that what we're doing is very much in line with the mission of Simplifying Programmable Logic Design. Again an obvious statement perhaps, but as long as we stay true to our mission and provide value, users will come to trust us. FPGAs can be sexy.

We got very curious about the Amazon AWS Startup Challenge and have been watching finalists' videos. Unfortunately the current round of applications requires Plunify to be registered in either the US, the UK, Germany or Israel. Being optimists, we'll try anyway ;)

Alright, back to work on the next feature...

Thanks for reading and have a good one!

Harnhua

Find a suitable reference design

2009-06-14T19:54:00.000-07:00

One of the first things many programmable logic developers do at the start of a project is to find a reference design--something containing most of what the final product would have, and more importantly, something that is proven to work.

This is akin to the modular design concept of not reinventing the wheel and building on an existing, working example. Important questions to ask might be:

Does this design contain all the interfaces I need?
Has it been tested in hardware and/or in simulation?
How much does it cost?
What do I need to test it (verify that it works as promised) e.g. additional software, hardware components?
Where/How do I obtain those extra components?

With the above in mind, we implemented a "Reference Design Search" to see if it can help our users.
Do have a look at the preliminary screenshots (on our Facebook page or the thumbnails below).
Happily, George, who sparked the idea in the first place, seems to like what he sees so far.

The flow is as follows:
First, the landing search page:
Enter something that you'd like to implement e.g. "embedded system USB"

Then, have a look at the initial results:
... shows how many reference designs and boards loosely match your search keywords.

Next, find out more about the designs and boards:
We'll be adding columns like Price and User Ratings soon, as well as information on all PLD vendors, not just the one you see in the screenshot.

Want to be more specific? Then try the advanced search, which we are still tweaking:
"Must have" and "Maybe" are the options presented for each feature, while a few guesses are made about the user's preferences. Those guesses are really the fun and difficult parts of this search feature--Kirvy is spending many hours on it to come up with something good.

Please let us know what you think, especially with regards to what aspects of a reference design you would like to know about, before choosing one.

Essentially, the most rewarding result of this feature would be helping a developer find good working examples.

Harnhua

Getting the moolah

2009-06-14T18:43:00.000-07:00

Finding money to fund one's endeavor--a topic close to entrepreneurs' hearts and blogged about almost incessantly. This is our experience, and please tell us about yours.

Fortunately, we have enough savings to bootstrap; which is not to say that we don't need extra investment, or that we didn't have to slash features to arrive at a realistic "can-launch" plan.

Knowing full well that we're still seed-stage, and that logically seed-stage companies normally don't attract many investors, plus being apprehensive of giving away too much equity at this point, we targeted the following, in descending order of priority:
- Government-type no-strings-attached grants: If they like us, they'll fund us; very few questions asked. Problem is, "like" is loosely-defined and infinitely-opaque here.
- Angel funding: Hallelujah!
- VCs: Epitome of the business world--no customers, no money. Well, that's a silly assertion I suppose, like saying fish don't swim without water.

Singapore has many initiatives to provide funding through government agencies. There has been a lot said about the pitfalls of such funding: lengthy, opaque application process (typical picture of government bureaucracy), non-consistent decision-making by non-committal stake-holders (mostly panelists from industry who aren't really responsible for the $$ they dish out), etc. Paul Graham wrote several insightful articles on the topic, as have many bloggers. TheFunded.com also covers many aspects of funding in general.

The first one we applied for was TECS. Spring Singapore provides a variety of schemes to finance budding entrepreneurs. We didn't get the money, and didn't particularly enjoy the whole experience because:

We waited 6 months for the entire process: application, business plan, presentation. Thankfully, the results were announced quickly.
There was little transparency--our questions to people other than the facilitators were never answered, although we, being the sellers, were naturally very responsive.
There was _no_ feedback on why we didn't make the cut.

Perhaps if we had gotten the money, I won't be complaining that much ; )
Now we understand why things are the way they are at Spring Singapore, and we sincerely hope for improvements.

On the bright side of things, the process itself was great, because:

It really helped us put our business plan together, especially the balance sheet forecast and the costs breakdown.
Nothing beats the real-world experience of pitching, albeit to the government. Wearing a suit in Singapore is a killer replacement for hot yoga.
Now we can share some good information with fellow entrepreneurs.

Would we apply again? Of course! One rejection motivates us even more, so watch this space : )
Good luck to all funding-seekers out there! We'd love to hear from you.

Harnhua

Origins

2009-05-10T08:40:00.000-07:00

A journey of a thousand miles begins with a single step.
千里之行，始於足下。
千里の道も一歩より。

And so we set out to make Plunify a real product that can hopefully make a difference in the world of Programmable Logic Design.

Plunify's origins can't quite be traced back precisely to those chats that Kirvy and I had in the onsen in 2008. Nor do they really date from the discussions with George, Sean and Mary in 2007. And probably not solely from when we started to hear complaints from web and FPGA users.

Thinking about it, I believe Plunify was born of hope, frustration and inspiration experienced by generations of pioneers--the brilliant people who invented the technology that we use to create Plunify today. We stand on the shoulders of giants and we'll do our best not to let you down.

Kirvy, Harnhua